The subject matter relates to semiconductor design technology, and more particularly to a high speed semiconductor memory device for preventing a drop of the level of an external voltage due to generation of high voltage to thereby ensure an effective data window.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a plurality of data pads 10, a data controller 20, a plurality of banks 30, and a plurality of high voltage generators 40 and 50. The data pads for a data input/output are disposed in a central region, each of which is composed by 8 bits. As illustrated the data pads are total 4 bytes. The data controller 20 receives an external voltage, generates a data clock, and controls data, which is output to the data pads, by using the data clock. The banks corresponding to each data pad are disposed above or below the respective data pad. One high voltage generator is provided for each bank in order to generate a high voltage VPP to be consumed by the bank.
As illustrated in FIG. 1, the data controller 20 and the data pads are disposed in a peripheral region of the semiconductor memory device.
FIG. 2 is a block diagram of the conventional high voltage generator 50.
Referring to FIG. 2, the high voltage generator 50 includes a level detecting unit 52, a first voltage generating unit 54, and a second voltage generating unit 56. The level detecting unit 52 detects a level of a high voltage VPP with respect to a reference voltage VREF to output a level detection signal PPEA. The first and the second voltage generating units 54 and 56 generate the high voltage VPP by charge-pumping an external voltage VDD periodically in response to the level detection signal PPEA.
Each of the voltage generating units 54 and 56, for example, the first voltage generating unit 54, includes an oscillation signal generator 54A and a high voltage pump 54B. The oscillation signal generator 54A generates an oscillation signal OSC having a predetermined period in response to the level detection signal PPEA. The high voltage pump 54B generates a high voltage VPP having a voltage level higher than the external voltage VDD by charge-pumping the external voltage VDD during an activation period of the oscillation signal OSC.
As illustrated in FIG. 2, the first and the second voltage generating units 54 and 56 share the level detecting unit 52 and are driven according to the level detection signal PPEA. However, each of the voltage generating units 54 and 56 can have separate level detecting units. In this case, the voltage generating units 54 and 56 operate as they do with a shared level detecting unit 52.
The operation of the voltage generating unit 54 will be described below.
The level detecting unit 52 activates the level detection signal PPEA when a level of the high voltage VPP is lower than a level of the reference voltage VREF. The oscillation signal generator 54A generates the oscillation signal OSC having a predetermined period during the activation period of the level detection signal PPEA. The high voltage pump 54B pumps the external voltage VDD during the activation period of the oscillation signal OSC, and generates a high voltage VPP having a voltage level higher than the external voltage VDD. When the oscillation signal generator 54A and the high voltage pump 54B are driven, the second voltage generating unit 56 is driven simultaneously to generate the high voltage VPP.
The above described process is repeated until the level of the high voltage VPP reaches the level of the reference voltage VREF.
The high voltage VPP is generated by charge-pumping the external voltage VDD, and the charge-pumping process makes up about 30% of a total external voltage consumption in the semiconductor memory device. Thus, when the high voltage VPP is generated, the level of the external voltage VDD drops. Such a drop will be described with reference to FIG. 3.
FIG. 3 is a signal timing diagram illustrating changes of an external voltage VDD and a data clock DT_CLK according to a driving of the high voltage generator of FIG. 2.
Referring to FIG. 3, when a level detection signal PPEA is activated, the high voltage pump 54B is driven to generate a high voltage VPP such that the external voltage VDD is consumed, and a level of the external voltage VDD drops.
Noise components, such as the drop of the level of the external voltage VDD, affect the data controller 20 driven by using the external voltage VDD as a driving voltage. For example, the amplitude of the data clock DT_CLK decreases and the duty cycle is distorted from 50% to 55%.
When the duty cycle of the data clock DT_CLK is distorted, since data are irregularly transferred to the data pad, time intervals between data packet arrivals become irregular. Due to the irregular time intervals, the size of an effective data window is reduced and the voltage generating unit abnormally operates at high data clock frequencies.
The high voltage generator 50, disposed between the banks 30, is a significant cause of the above described effect, because the data controller 20 disposed in a central region of the semiconductor memory device is closer to the high voltage generator 50 than the high voltage generator 40.